Pei-HsinHo
CTO of UniVista Industrial Software Group

Keynote：The Future of RTL Design and Verification: A Vision for Collaborative Human Experts, Generative AI, and EDA Engines

Abstract: The accelerating complexity of semiconductor designs has exposed the limitations of traditional RTL design and verification methodologies. This keynote explores a transformative methodology for the future of RTL design, where the collaboration between human experts, generative AI, and EDA engines converges to overcome these limitations and reshape the design and verification landscape.
Generative AI can interpret design specifications written in natural languages, as well as waveforms and finite-state-machine diagrams. When integrated with powerful EDA engines such as RTL synthesis, simulation, formal verification, and debugging tools, this collaboration enables (1) automatic generation of multiple versions of synthesizable Verilog code, providing different timing and area tradeoffs for the human expert to choose, (2) automatic detection and correction of both syntactic and semantic RTL bugs, and (3) semi-automatic creation of constrained random simulation testbenches with built-in coverage goals and assertions. These capabilities not only streamline the design process but also generate high-quality RTL designs ready for synthesis and physical implementation.
Through real-world examples, this talk will demonstrate how this collaborative workflow can radically accelerate the design and verification process, empowering design experts to focus on higher-value tasks such as algorithmic and architectural innovations. Join us as we explore the next frontier in RTL design and verification, where human intelligence, AI, and EDA engines work in unison to drive breakthrough innovations in chip design.