Keynote

 

Title: Computational Logistics for Intelligent System Design
Speaker: Simon Chang
Thanks to our Sponsor: Cadence

Title: Next Generation of EDA                                
Speaker: Luke Yang
Thanks to our Sponsor: X-EPIC

 

 

Poster Session

NO.001: 可适用于大规模数通芯片UVM验证平台自动搭建的eSim开发
Speaker: Ankui Ge

NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet
Speaker: Xia Li

NO.003: 基于开源工具的RISC-V处理器核验证
Speaker: Yanbing Xu

NO.005: Improvement of chip verification automation technology
Speaker: Yao Ma

NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC
Speaker: Shuhui Wang

NO.008: LiteX: a novel open source framework for SoC
Speaker: Feng Li

NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area
Speaker: Minqi Bao

NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification
Speaker: Yeung Ping

NO.011: Completely Release the Power of Verification IP–A Step-by-Step Guidance for In-House IP Development
Speaker: Bin Liu

NO.012: How Fast Can You Run SLEC for Verifying Design Optimizations and Bug Fixes
Speaker: Francisco Chen

NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification
Speaker: Sarah Li

NO.014: An Intelligent SOC Verification Platform
Speaker: Deyong Yang

   

NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores
Speaker: Weiwei Chen

   

 


Paper Session

Paper Session 1: 可适用于大规模数通芯片性能分析工具开发
Speaker: Dinglai He

Paper Session 2: UVM is Now IEEE1800.2-2020 Standard: A 2020 Adoption Primer
Speaker: Roman Wang

Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verification
Speaker: Jinghui Li

Paper Session 4:   Unified Automation Verification Management Approach
Speaker: Wenbo Liu

Paper Session 5: Cache Coherency Verification for Multi-Core Processors Based on the PSS
Speaker: Yang Yang

Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc Design
Speaker: Yuxin You

 

Paper Session 7: Best Practice Coding Assertion IP (AIP) to Get More Predictable Results
Speaker: Leon Yin

Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification Closure
Speaker: Yuxin You

 



Short Workshop

Short Workshop 1: The New Power Perspective – Realistic Workloads – Real Results
Speaker: Brian Li
Thanks to our Sponsor: Synopsys

Short Workshop 2: Smarter Verification Management
Speaker: David Zhang
Thanks to our Sponsor: Cadence

Short Workshop 3: Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design Methodology
Speaker: Wenbo Zheng
Thanks to our Sponsor: SIEMENS

Short Workshop 4: Applying Big Data to Next-Generation Coverage Analysis and Closure
Speaker: Francisco Chen
Thanks to our Sponsor: SIEMENS

Short Workshop 5: 5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met IC
Speaker: David Hwang, Shichao Gao, Jimmy Sun
Thanks to our Sponsor: X-EPIC

Short Workshop 6: Fast forward Software Development using Advanced Hybrid Technologies
Speaker: Xiaowei Pan
Thanks to our Sponsor: Synopsys

 

Short Workshop 7: PCIe Gen5 Validation - The Real World
Speaker: Yuan Chen
Thanks to our Sponsor: Synopsys

Short Workshop 8:  Veloce HYCON: Software-enabled SoC verification and validation on day 1
Speaker: Jeffrey Chen
Thanks to our Sponsor: SIEMENS

 



Tutorial

   

Title: Acceleration Startup Design & Verification
Speaker: Tim Sun
Thanks to our Sponsor: Cadence

 

 

Copyright © 2021 DVCon all rights reserved. Site designed, developed and maintained by MCI China

 Privacy Statement