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Dear friends,

I am honored to be the chairman of the DVCon China again. On behalf of the whole steering committee, we welcome all the old and new friends to join us. As a platform focus on technology, we’d like to bring you latest update from the industry, new ideas and new practices from engineers all over the country.

In 2021, DVCon China got another record of participants. People were shocked by how hot the industry was. Most of my friends were busy on their chip tapeouts or publishing their new EDA tools. Unfortunately, we see some ebb and flow of industry these days. But why not take it as an opportunity to review our work, are you really doing something cool or just homogenous work?

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DVCon China 2023 General Chair

PeiYu Liu

2023 Keynote Speakers

EDA 2.0 – Leveraging AI to Achieve The Next 10x

IC device complexity continues to increase, driven by expanding demand for SoCs across industries like hyperscale compute, automotive, IoT, aerospace, and mobile. Increased complexity and demand for devices has resulted in more design starts, with not enough engineering resources to meet the demand. As Artificial Intelligence and Machine Learning become more and more accessible across the technology landscape, EDA has the opportunity to leverage these technologies to increase overall productivity through both automation, and catalyzation of the human in the loop. Cadence keynote speech will discuss this IC landscape, and how AI can help EDA drive the next 10x increase in engineering productivity.

VP of System Verifications Group Cadence Design Systems, Inc.

Yogesh Goel

Speaker's Bio >

System Design with Agile Verification and Continuous Acceleration

Chip design is increasingly shifting towards system-level application as the core focus. A typical example is the popular STCO (System Technology Cooperative Optimization) methodology in recent years. However, at the same time, the scale of design and verification is also growing, requiring designers to enter the system-level verification earlier and faster. They are becoming increasingly dependent on better Electronic Design Automation (EDA) tools to provide system-level simulation performance and debugging capabilities.

This new trend imposes higher demands on EDA tools, especially concerning verification. XEPIC Technology, based on the concepts of agile verification and continuous acceleration, continuously innovates on XEPIC FusionVerify platform. We provide earlier, faster, and more comprehensive verification solutions tailored to the needs of application-level design verification.

Product and Business Planning Senior Director of XEPIC

Luke Yang

Speaker's Bio >

ABOUT DVCON

About DVCon China

DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley.

In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in China, this highly technical conference is organized to invite industry experts to learn and share best practices on:
1.The application of system-level design and verification languages such as SystemC, SystemVerilog or e 2.The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL) 3.Verification methodologies based on the Universal Verification Methodology (UVM)

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