First of all, we want to say a big thank you for your support of DVCon China. We made a difficult decision to cancel DVCon China 2020 because of the novel coronavirus outbreak. Thank you for understanding and patience, now we’re back. On behalf of the whole steering committee, I welcome all our old and new friends to join us.
We have a strong TPC with experts from many famous companies this year, and our vision is to provide you a platform to hear the latest update from the industry and exchange ideas with engineers all over the country.MORE >
Computational software is the enabling technology upon which all these drivers rely, and it is innovation in computational software that is helping shape the future. Today’s computational software applications span numerous industries, including semiconductors, systems, weather prediction, scientific software, and financial, medical, and business analytics.
This keynote will lead use to understand better the innovation of computational software to contribute on the intelligent system design.
In the past 30 years IC design tools evolved to today's EDA process. However, the level of automation and intelligence at current EDA is still far from enough to support rapidly growing needs for new hardware chips. X-EPIC brings the concept of EDA 2.0 as next generation IC design platform to reduce human dependency, increase design productivity, and equip the industry with an easier process from application system requirement to new hardware chips and platforms.
DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley.
In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in China, this highly technical conference is organized to invite industry experts to learn and share best practices on:
1.The application of system-level design and verification languages such as SystemC, SystemVerilog or e 2.The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL) 3.Verification methodologies based on the Universal Verification Methodology (UVM)
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