在2021年，DVCon China参会人数达到了历史新高，每个人都感受到了行业的热度。我的朋友们都很忙，要么忙于芯片的TO，要么忙于新EDA工具的推出。很不幸，最近的一段时间里行业遇到了一些起伏。但是何不把这看作是一次重新审视我们的工作的机会呢？疲于奔命的两年，我们究竟有多少是创造性的劳动又有多少是同质化的重复？MORE >
IC device complexity continues to increase, driven by expanding demand for SoCs across industries like hyperscale compute, automotive, IoT, aerospace, and mobile. Increased complexity and demand for devices has resulted in more design starts, with not enough engineering resources to meet the demand. As Artificial Intelligence and Machine Learning become more and more accessible across the technology landscape, EDA has the opportunity to leverage these technologies to increase overall productivity through both automation, and catalyzation of the human in the loop. Cadence keynote speech will discuss this IC landscape, and how AI can help EDA drive the next 10x increase in engineering productivity.
Chip design is increasingly shifting towards system-level application as the core focus. A typical example is the popular STCO (System Technology Cooperative Optimization) methodology in recent years. However, at the same time, the scale of design and verification is also growing, requiring designers to enter the system-level verification earlier and faster. They are becoming increasingly dependent on better Electronic Design Automation (EDA) tools to provide system-level simulation performance and debugging capabilities.
This new trend imposes higher demands on EDA tools, especially concerning verification. XEPIC Technology, based on the concepts of agile verification and continuous acceleration, continuously innovates on XEPIC FusionVerify platform. We provide earlier, faster, and more comprehensive verification solutions tailored to the needs of application-level design verification.
DVCon China2022 会务组
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