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DVCon China is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C, C++, PERL, Tcl, and Python. Tools and methodologies include the use of testbench automation, portable stimulus, hardware-assisted verification, hardware/software co-verification, assertion-based  and  formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.

DVCon China is looking for short workshops to encourage greater sponsorship participation from companies and exhibitors, especially smaller organizations at an affordable level.

DVCon China is looking for short workshop topics that are current, have a high level of interest and offer strong continuing educational content. 

Short Workshop sponsors reach a captive audience during the 45-minute educational sessions and have the opportunity to follow-up with attendees during breaks, at the exhibits, and following the event.

DVCon is a highly-targeted venue for engineers addressing major design and verification issues. 


Sponsorship Includes:

  • A 45-minute Short Workshop presentation on Wednesday
  • Short Workshop content will be publicized via DVCon website, Conference Program and in the Opening Session
  • Other promotion items like banners, flyers, gift items, etc may be distributed during the Short Workshop

For more information concerning the conference, please contact the conference management, Elyn Han at


  • Please include in the proposal the name of the companies that will be sponsoring the short workshop
  • Include suggested presenters names, affiliations and biographies
  • Your proposal should be a short abstract of the short workshop, two to five paragraphs, 1,000 words maximum
  • Please indicate if this short workshop is a “hands-on” session or lecture format
  • Any necessary additional hardware that you may require must be provided by the short workshop organizers


  • SystemVerilog for Verification and/or Design
  • SystemC /C/C++ Design and/or Verification of systems.
  • SoC and Software-driven Verification
  • Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
  • Coverage-driven Verification
  • High-level Synthesis
  • Low-power Design and Verification techniques
  • Secure/Encrypted IP-based SoC design methods
  • Debug for design and verification
  • Mixed-signal modeling and verification
  • Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT)
  • Functional Safety
  • Security
  • Embedded software verification
  • Hardware/Software Co-development
  • Verification Productivity Methods
  • Formal Methodology and Static Analysis
  • Emulation
  • Post SI Debug
  • FPGA Prototyping
  • Moving from proprietary solutions to standards-based design and verification
  • Portable Stimulus
  • Application-based design verification challenges, techniques


  • July 21, 2023: Short Workshop proposals due
  • August 4, 2023: Accept/reject notification
  • August 23, 2023: All Short Workshop content due for Conference Program and website (title, abstract, speaker names, affiliations and biographies)
  • September 6, 2023: Draft Presentation slides due to DVCon Tutorial/Short Workshop Chair
  • September 19,2023: Final slides due for final production for attendee distribution

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