Keynote
 |
 |
|
|
Title: Computational Logistics for Intelligent System Design |
Title: Next Generation of EDA |
Poster Session
 |
 |
 |
|
NO.001: 可适用于大规模数通芯片UVM验证平台自动搭建的eSim开发 |
NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet |
NO.003: 基于开源工具的RISC-V处理器核验证 |
 |
 |
 |
|
NO.005: Improvement of chip verification automation technology |
NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC |
NO.008: LiteX: a novel open source framework for SoC |
 |
 |
 |
|
NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area |
NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification |
NO.011: Completely Release the Power of Verification IP–A Step-by-Step Guidance for In-House IP Development |
 |
 |
 |
|
NO.012: How Fast Can You Run SLEC for Verifying Design Optimizations and Bug Fixes |
NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification |
NO.014: An Intelligent SOC Verification Platform |
 |
||
|
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores |
Paper Session
 |
 |
 |
|
Paper Session 1: 可适用于大规模数通芯片性能分析工具开发 |
Paper Session 2: UVM is Now IEEE1800.2-2020 Standard: A 2020 Adoption Primer |
Paper Session 3: Co-simulation platform of SystemC and System-Verilog for algorithm verification |
 |
 |
 |
|
Paper Session 4: Unified Automation Verification Management Approach |
Paper Session 5: Cache Coherency Verification for Multi-Core Processors Based on the PSS |
Paper Session 6: High Reliability Reset Domain Checking Solution for the Modern Soc Design |
 |
 |
|
|
Paper Session 7: Best Practice Coding Assertion IP (AIP) to Get More Predictable Results |
Paper Session 8: Advanced Techniques for Enabling Gate-level CDC Verification Closure |
|
Short Workshop
 |
 |
 |
|
Short Workshop 1: The New Power Perspective – Realistic Workloads – Real Results |
Short Workshop 2: Smarter Verification Management |
Short Workshop 3: Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design Methodology |
|
|
 |
 |
|
Short Workshop 4: Applying Big Data to Next-Generation Coverage Analysis and Closure |
Short Workshop 5： 5.1 Smart Verification leveraging PSS; 5.2 When Automotive FuSa Met IC |
Short Workshop 6: Fast forward Software Development using Advanced Hybrid Technologies |
 |
 |
|
|
Short Workshop 7: PCIe Gen5 Validation - The Real World |
Short Workshop 8: Veloce HYCON: Software-enabled SoC verification and validation on day 1 |
|
Tutorial
 |
||
|
Title: Acceleration Startup Design & Verification |
|
|
loading......