![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120255767.jpg) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120256086.png) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120256421.png) |
NO.001: 可适用于大规模数通芯片UVM验证平台自动搭建的eSim开发
Speaker: Ankui Ge
|
NO.002: Accurate Charge-pump Regulator Modeling using SV EEnet
Speaker: Xia Li
|
NO.003: 基于开源工具的RISC-V处理器核验证
Speaker: Yanbing Xu
|
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120256737.png) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120256936.jpg) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120257243.jpg) |
NO.005: Improvement of chip verification automation technology
Speaker: Yao Ma
|
NO.006: A Systematic IP Verification Solution of Complex Memory Management for Storage SOC
Speaker: Shuhui Wang
|
NO.008: LiteX: a novel open source framework for SoC
Speaker: Feng Li
|
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120257587.png) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120258190.jpg) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120258545.jpg) |
NO.009: Transaction Equivalence Formal Check (DPV) in Video Algorithm/FPU/AI Area
Speaker: Minqi Bao
|
NO.010: Silicon Bug Hunt with“Deep Sea Fishing”Formal Verification
Speaker: Yeung Ping
|
NO.011: Completely Release the Power of Verification IP–A Step-by-Step Guidance for In-House IP Development
Speaker: Bin Liu
|
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120258865.jpg) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120259215.png) |
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120259889.png) |
NO.012: How Fast Can You Run SLEC for Verifying Design Optimizations and Bug Fixes
Speaker: Francisco Chen
|
NO.013: Sequential Equivalence Checking Beyond Clock Gating Verification
Speaker: Sarah Li
|
NO.014: An Intelligent SOC Verification Platform
Speaker: Deyong Yang
|
![](/assets/userfiles/sys_eb538c1c-65ff-4e82-8e6a-a1ef01127fed/images/remote/20210702120300471.jpg) |
|
|
NO.015: A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores
Speaker: Weiwei Chen
|
|
|