Paper Session 1: A Multi-Agent Generative AI Framework for IC Module-Level Verification Automation

Paper Session 2: Formal Verification Sign-off Methodology for Pin Multiplexing Based on Jasper CONN

Paper Session 3: Scalable Software Testing in Virtual Platforms: Leveraging SystemC, QEMU and Containerization

Paper Session 4: Approaching Zero DPPM with Functional and Test Coverage Patterns Combined Methodology

Paper Session 5: SLEG: A LLM-based SVA Evaluation and Generation System

Paper Session 7: A System-Level Random Verification Method for Multi-threaded Processors

Paper Session 8: Multi-cycle path verification method based on TCM

Paper Session 10: A Practical High Level Verification Methodology for HLS design

Paper Session 11: Automated SVA Generation with LLMs

Short Workshop 1: Avery Verification IP: Delivering Accelerated Confidence in Complex IC Verification

Short Workshop 3: Modernizing the Hardware/Software Interface

Short Workshop 4: Introducing Smart Verification Unleashing the Potential of AI Within Functional Verification