Title: EDA 2.0 – Leveraging AI to Achieve The Next 10x
Speaker:  Yogesh Goel
Thanks to our Sponsor: Cadence

Title: System Design with Agile Verification and Continuous Acceleration                                
Speaker: Luke Yang
Thanks to our Sponsor: X-EPIC

Paper Session 1:Use Save and Restore methodology tospeed-up regression
Speaker: Wenping Guo Ge

Paper Session 2:An advanced method for RISC-V load-store andregister hazard verification, leveraging PSS.
Speaker: Adnan Hamid

Paper Session 3:Exploring Formal Verification: A Journey ThroughMaturity Levels and Case Studies, with a Glimpse intothe Future of Assertion Creation with the Power of GPT
Speaker: Shawn Zhang

Paper Session 4: 一种用于 SOC 芯片的联合验证方法
Speaker: Tieniu Chen

Paper Session 5: PHY Verification ip
Speaker: Pancholi Mrunal

Paper Session 6: BEYOND UVM
Speaker: Feng Li

Paper Session 7: Functional Coverage Analysis of Mixed.Signal Verification Based on Correlation Modeling
Speaker: Jiagang Xu

Paper Session 8: Detecting Implementation Glitches in Gate-levelDesigns Using Advanced Hierarchical Techniques
Speaker: Yuxin You

Paper Session 9: Atomic Sequence And Multilayer RegressionStrategy Based On Saving And RestoringMethodology
Speaker: Alvin Zhang

Paper Session 10: Agile SoC Design and Verification usingSpinal HDL and Cocotb
Speaker: Pu Wang

Paper Session 11: Python-based emerging DSLs for FOSS EDA
Speaker: Feng Li

Paper Session 12: 基于 PSS 中间层的验证平台架构设计
Speaker: Lei Wang

NO 001: 一种并行验证加速架构及应用 --从Chiplet到Simlet
Speaker: 张栗榕 王锋 郑文刚 王灌锋

NO 002: Intelligent Approach to Shift-Left the Identification of CDC Convergence Issues During RTL Simulation
Speaker: Charles Lou, Susan Xie,

NO 005: Generating UVM Testbenches for Fun and Productivity
Speaker: Rich Edelman and Sanna Zhou

NO 006: Eliminate Silicon Failures by 100% CDC Signoff Confidence Using Static-Aware Synthesis Followed by Netlist CDC Verification
Speaker: Yujing Feng

NO 007: 基于Python和事务级的Meta-HVL验证框架
Speaker: 林学，赖晓铮，杨晔

NO 008: 高效敏捷 SoC 验证和性能评估平台– FastSoC
Speaker: 袁泽旭，赵瑞君，高勇

NO 009: 智能高效的代码发布与自动回归平台
Speaker: 王兴耀, 郑俊浩

NO 010: Scale IP UVC in SOC testbench
Speaker: Lingkai Shi

NO 011: ASV多场景测试激励自动生成系统
Speaker: 张栗榕、王锋、张烨晨、贺岩

NO 015: Explore the Potential of AI to Accelerate Formal Verification
Speaker: Yongtai Cheng

Short Workshop 1:Catapult HLS & HLV Platform - EnablingAgile And High Quality IC Design
Speaker: Wenbo Zheng

Short Workshop 2:Al-Powered Verification Debug - Faster and MoreAccurate Root Cause Analysis
Speaker: Yuesen Lu

Short Workshop 3:Cadence'FMEDA-Driven Analog/Mixed-Signal andDigital Safety Design
Speaker: Xinwei Wu

Short Workshop 4:Heterogeneous Verification to Acceleratethe Innovative SoC Design
Speaker: Jimmy Chen

Short Workshop 5:Austemper Kaleidoscope - Facilitating TheAdvanced Fault Campaign Strategies ForFunctional Safety Verification
Speaker: Kara Liu

Short Workshop 6:Automation of Realisation Layer forIP/SoC using PSS & SystemRDL
Speaker: Sudhir Bisht

Short Workshop 7: Ensuring System-Level Coherency: ASystem-Level Framework forVerification and Measurement
Speaker: Qingli He

Short Workshop 8:Escalating requirements for SoC verification usingreal software applications - extending emulationand prototyping for Power/Performance/FuSavalidation
Speaker: Viiay Chobisa

Short Workshop 9:Revolutionizing IC Design Verification: HarnessingEmulation and Prototyping for Design Success
Speaker: Qinvi Liu

Short Workshop 10:Advanced Core/SoC Verification forRIsc-V and Other Cores
Speaker: Adnan Hamid

Tutorial 1:
Cadence' Al Driven VerificationPlatform - Verisium Platform
Thanks to our Sponsor: Jiankun Zhang,Curtis Tsai