Leveraging Virtual Prototypes from Concept to Silicon

This tutorial is targeting to describe ARM Models solutions regarding of Virtual Prototype technology. The tutorial will comprise three major parts: ARM Fast model for pre-silicon SW development, ARM Cycle model for System Exploration and Performance analysis, and Hybrid Virtual Prototyping for more use case like SW driven verification. 

Portable Test and Stimulus: The Next Level of Verification Productivity is Here

Why reinvent the wheel? Up until now, verification teams had been unable to reuse tests as their efforts progressed from virtual platforms to RTL, block-level to system-level or from simulation to emulation, prototyping or silicon. The advent of UVM, constrained-random verification and functional coverage improved the reusability of portions of the verification environment, but these advances have not been able to enable reuse of verification intent throughout the product development process.

Smarter Verification – Beyond Brute Force

To optimize development schedules for advanced hardware/software developments, a combination of best in class engines for formal verification, simulation, emulation and FPGA based prototyping is required. Users are carefully optimizing the utilization of verification cycles executed on the various engines.

Poster Session

Exhibits

Come to the DVCon China Expo and you will:

Meet vendors of design and verification tools, IP/VIP and services! Spend quality time with the vendors you most want to meet! Discover and learn about the latest products and services!

The Next Big Thing in Design Driving the Next Big Wave in Verification

Our industry has experienced remarkable breakthroughs in computing, networking, and communication technology in recent years. Yet, it is the convergence of these technologies that is driving the next big thing in innovation related to IoT and autonomous systems. And it is also driving the need for new approaches to verify today’s complex systems. In this keynote, Harry Foster shares a holistic view of the next big wave in verification.

Industry’s Next Challenge: The Petacycle Challenge

This keynote highlights how new growth segments, such as Automotive, IoT, Networking, 5G Mobile, etc. are fundamentally changing the requirements for verification. The keynote will emphasize how addressing the SoC verification, software bring-up and validation needed for these segments will change the nature of verification technologies and solutions. 

Opening Ceremony

Join us as we set the stage for the 2018 DVCon Conference and Exhibition. DVCon's Steering Committee will highlight the conferences events.

The Big Data Revolution Beautiful Servant or Dangerous Monster?

The world is experiencing the revolution of information, humanity shifting the hegemony from Science onto Data.

Cogita is a technological pathway that controls the data and creates measuring perceptions that do not forego or leave aside the human consciousness.
Cogita is a data screening, processing and visualization tool that targets ASIC and FPGA simulation based debug.

What Makes a Good Code Coverage Tool for HLS?

Closing code coverage in RTL is one of the toughest verification challenges and moving to High-Level Synthesis (HLS) hasn’t made coverage closure any easier. This workshop highlights the fundamental difference between closing coverage for software and HLS models, and how Catapult Coverage from Mentor, A Siemens Business lets you close RTL coverage on the HLS model.
 

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