How long does it take you to bring up your multi-FPGA, or even single-FPGA prototype?
2 months, 3 months, more? If it takes you longer than 2 WEEKS, then you should attend this session and learn how you can reduce the bring-up time from months to weeks!
In this workshop you will learn how Cadence’s new Protium S1 system can make FPGA-based prototyping more productive and easier to use than ever before. We will walk you through the steps to implement a complete SoC design with embedded processor, memory and peripherals into a multi-FPGA prototyping system.
The size and complexity of FPGA designs are getting larger with each design and designers are asked to achieve more with less. As the complexity grows, FPGA designers are under increasing pressure to accelerate designs, which has the potential cause more bug escapes. This means that FPGA designers need to segment the design flow into multiple phases to gain productivity improvements at each phase.
Modern verification methodologies incorporate multiple coverage solutions. These range from functional to structural coverage, leverage various coverage models and operate using varied technologies in both the simulation and formal process. The main purpose of these coverage solutions is to establish a signoff metric that indicates when enough verification has been performed. However, as coverage approaches have evolved, new use models have emerged for these tools that increases their value in the verification process.
Modern SoC size and complexity grow too fast, which brings a big challenge to strive for a qualified verification through the module level to the system level. In this session, we will address the most concerned challenges in SOC level verification. such as performance monitor/analysis, functional coverage, simulation efficiency.
DRAM memory controllers have gained a
lot of popularity in recent years. They are widely used
in applications ranging from smart phones to high
performance computers. These applications requires
large amount of memory accessing. However, memorywall
is still a bottleneck. In this session part1, we introduce the
most recent techniques used to enhance DRAM
Memory controllers in terms of power, capacity, latency
and bandwidth. In this session part2 we cover register && memory sequence seamless reuse in IP and SoC verification.
In this session, we will cover IP-level Reference Modeling & Dynamic Configurable Test-Adaptive Testbench Infrastructure for SoC Verification
Verification methodology is getting more and more important when it comes to IP&& SoC verification. In this session we will discuss Formal verification && Emulator methodology. the one big challenge for Formal verification is how to handle inconclusive assertion. In this session part1, we cover the methodology and experience how to close inconclusive assertion proven. Hardware accelerator is commonly used more and more in a lot of company. In this session part2, we cover how to conquer complex SOC test sequences with Emulator.
As the transportation industry continues to increase the amount of electronics and embedded software included in its products, systems and semiconductor makers must now consider the fault tolerance of their product offerings to customers in this rapidly growing market. Fortunately, the ISO 26262 standard defines straightforward metrics for evaluating the "safeness" of a design by defining safety goals, safety mechanisms, and fault metrics.