Have you ever spent weeks or even months trying to reproduce a design bug that only shows up sporadically, and therefore extremely hard to catch? Many people can tell you their horror stories of trying to catch these bugs, which turned out to be related to reset metastability.
Hardware/Software Interface (HSI) plays a key role in the development of SoCs. This interface is best described in a textual format using the SystemRDL – an Accellera Standard. Recently version 2.0 of the SystemRDL has been released. Agnisys will provide detailed hands-on training on SystemRDL and how it impacts the SoC development in many areas – RTL, UVM, Firmware etc.