Performance & Efficiency

Modern SoC size and complexity grow too fast, which brings a big challenge to strive for a qualified verification through the module level to the system level. In this session, we will address the most concerned challenges in SOC level verification. such as performance monitor/analysis, functional coverage, simulation efficiency.

Memory Design and Verification

DRAM memory controllers have gained a
lot of popularity in recent years. They are widely used
in applications ranging from smart phones to high
performance computers. These applications requires
large amount of memory accessing. However, memorywall
is still a bottleneck. In this session part1, we introduce the
most recent techniques used to enhance DRAM
Memory controllers in terms of power, capacity, latency
and bandwidth. In this session part2 we cover register && memory sequence seamless reuse in IP and SoC verification.

State Based Reference Model Innovation and Dynamic Configurable Testbench in SOC

In this session, we will cover IP-level Reference Modeling & Dynamic Configurable Test-Adaptive Testbench Infrastructure for SoC Verification

Verification Methodology: Formal & Emulator

Verification methodology is getting more and more important when it comes to IP&& SoC verification. In this session we will discuss Formal verification && Emulator methodology. the one big challenge for Formal verification is how to handle inconclusive assertion. In this session part1, we cover the methodology and experience how to close inconclusive assertion proven. Hardware accelerator is commonly used more and more in a lot of company. In this session part2, we cover how to conquer complex SOC test sequences with Emulator.

Performance Estimation and Optimazation using Synopsys Platform Architect

Accurate performance estimation in early stage is a challenge work. The issue became much more difficult when a new topology or peripherals introduced to the project. Platform Architect allows engineers to do simulation at the beginning of the project without RTL design and software. The combination of task workload and hardware architecture could simulate different scenarios according to different requirements.

How to Stay Out of the News with ISO26262-Compliant Verification

As the transportation industry continues to increase the amount of electronics and embedded software included in its products, systems and semiconductor makers must now consider the fault tolerance of their product offerings to customers in this rapidly growing market. Fortunately, the ISO 26262 standard defines straightforward metrics for evaluating the "safeness" of a design by defining safety goals, safety mechanisms, and fault metrics.

Leveraging Virtual Prototypes from Concept to Silicon

This tutorial is targeting to describe ARM Models solutions regarding of Virtual Prototype technology. The tutorial will comprise three major parts: ARM Fast model for pre-silicon SW development, ARM Cycle model for System Exploration and Performance analysis, and Hybrid Virtual Prototyping for more use case like SW driven verification. 

Portable Test and Stimulus: The Next Level of Verification Productivity is Here

Why reinvent the wheel? Up until now, verification teams had been unable to reuse tests as their efforts progressed from virtual platforms to RTL, block-level to system-level or from simulation to emulation, prototyping or silicon. The advent of UVM, constrained-random verification and functional coverage improved the reusability of portions of the verification environment, but these advances have not been able to enable reuse of verification intent throughout the product development process.

Cadence Keynote TBD

Poster Session


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