Memory Design and Verification

DRAM memory controllers have gained a
lot of popularity in recent years. They are widely used
in applications ranging from smart phones to high
performance computers. These applications requires
large amount of memory accessing. However, memorywall
is still a bottleneck. In this session part1, we introduce the
most recent techniques used to enhance DRAM
Memory controllers in terms of power, capacity, latency
and bandwidth. In this session part2 we cover register && memory sequence seamless reuse in IP and SoC verification.

Event ID: 
3931efb3-9224-430c-83b2-ea748fe1d22d
Event Type: 
Regular Session
Location: 
Ballroom A
Event Time: 
Wednesday, April 18, 2018 -
16:00 to 17:00
Session Number: 
3
Session Number: 
3
confID: 
250