Shanghai, China


2018 Keynote Address - Smarter Verification – Beyond Brute Force

2018 Keynote Address - Smarter Verification – Beyond Brute Force

To optimize development schedules for advanced hardware/software developments, a combination of best in class engines for formal verification, simulation, emulation and FPGA based prototyping is required. Users are carefully optimizing the utilization of verification cycles executed on the various engines. Beyond brute force, beyond simply faster execution, a verification fabric offering verification management, debug, verification IP and portable stimulus for software driven SoC verification is poised to really increase “smartness” of verification and to guide users in their quest to best utilize every verification option they are given, in sequence and in combination. This keynote will introduce the latest trends driving the future of verification and provide a peak into the latest and upcoming improvements in efficient integration of the engines to increase verification productivity.



Michał Siwiński Cadence Design Systems

Michał Siwiński is the Vice President of Product Management and Operations for the System & Verification Group at Cadence Design Systems. His responsibilities include strategy, product portfolio & roadmap, business development, ecosystem and operations for the Cadence Verification Suite, delivery double-digit growth. The Suite includes JasperGold® formal verification, Xcelium™ parallel simulation, Palladium® emulation, and Protium™ FPGA prototyping core engines. Additionally, it includes Verification IP, Perspec™ tests, vManger™ metrics, and Indago™ debug as the multi-engine verification fabrics. Siwiński is also driving Cloud and Application-optimized verifications to address challenges faced by systems and semi companies across Mobile, Networking, Server, Consumer, IoT, Automotive, Aero & Defense, and other verticals, as part of the Cadence System Design Enablement strategy.

Previously at Cadence, Siwiński held various product management and product marketing positions, including responsibilities for functional verification, front-end digital, PCB & IC packaging, and starting the IP business. He also led the creation and deployment of key industry initiatives such the Universal Verification Methodology (UVM) from concept to industry standardization, establishing new verification technology sub-segments, and enabling the shift from point tools to integrated end-to-end verification platforms.

Siwiński joined Cadence via the acquisition of Verplex Systems, where he was responsible for the formal property checking product line, and held various roles in product and technical marketing, product engineering management, product validation, and field applications. Prior to Verplex, Siwiński performed digital design consulting services at Mentor Graphics, Inc.

Siwiński received his Bachelor of Science dual degree in Electrical Engineering and Computer Science from the University of California at Berkeley.