April 18th, 2018

Doubletree by Hilton Shanghai-Pudong

Welcome Message from the General Chair

Welcome Message from the General Chair

Dear friends,
Welcome to the 2nd Design and Verification Conference and Exhibition China (DVCon China).
 
Thanks to Accellera, the members of DVCon China committee, and all community friends from semiconductor industry and academy, DVCon China 2017 was the first DVCon held in China, and was a great success. 6 tutorials from Accellera, Cadence, Mentor and Synopsys, 8 technical papers, and dozens of poster papers covering Simulation, Emulation, Debug, Formal, System C, Low Power, Portable Stimulus, Virtual Prototyping, UVM, Fault Simulation, Machine Learning, and more, gave the 200+ attendees a wonderful day in Shanghai. Now DVCon China 2018 is coming.
 
As Dr. Wally Rhines, President and CEO of Mentor, a Siemens Business shared with us in the DVCon China 2017 opening keynote, Chinese engineers adapt new design and verification technologies faster worldwide. In this golden era for the China semiconductor industry, it’s the pleasure of DVCon China committee members to continue providing this platform of new design and verification methodologies, new technologies, new trends, and experiences sharing to more Chinese IC engineers. Attendees can attend various technical sections covering System Level Design, Verification & Validation, IP Reuse and Design Automation, Mixed-Signal, Low Power, High Performance design and Verification, virtual prototyping among other topics, as well as visit the exhibition booths and communicate with the experts from different companies.
 
Looking forward to meeting you all in DVCon China 2018.
 
Sincerely yours,
Jinnan Huang
DVCon China 2018 General Chair