15 April 2020

Shanghai, China

Welcome Message from the General Chair

Welcome Message from the General Chair

I am honored to be the chairman of the 4th DVCon China again, and together with the members of the organizing committee, provide IC industry engineers from all over the country with a platform for technical exchanges.
 
The DVCon China 2019 conference was very successful. We received more papers than before, and we received more attention and recognition from the industry. We hope to inject this successful conference experience into the preparation work for the next year conference.
 
While new products appear in the IC market, we have received more diversified solutions in the chip verification solution. For example, testbench automation and test vector automation solutions are improving verification efficiency, and the coverage consistency requirement also makes the coverage integration of the formal and the simulation faster.
 
However, we find that the complexity and the efficiency gap of verification are still expanding. We are introducing new tools and methods to make up for these gaps, but in addition to engineers needing to learn to master new tools and methods, we are also considering how to make new solutions improve the efficiency of verification and no longer bring new workload to engineers.
 
As a result, we have introduced portable stimulus standard that are designed to describe more abstract operations based on existing system-level UVM and C tests, and then enable test reuse at different stages of development. Meanwhile, we are also discovering more value in formal verification, allowing them to perform more reliable and efficient verification than simulation in some scenarios.
 
Faced with so many different tools and methods, the verification engineers need to be like a brave and wise general, choose the right solution in the intense project execution, and then report the results of the different camps together. The ability of the verification engineer is constantly extending along with the size of the chip.
 
Even if a verification engineer is becoming more proficient in the project and has raised many new challenges, we still need to grasp the essence of things, look for common and customized verification solutions, and which are positive for improving verification efficiency. These bright points in our daily work will also become shining stars at the annual DVCon conference, which will become a roadmap for guiding verification engineers.
 
I am very willing to hang up the stars with the friends of the technical committee of this conference, and I hope more new verification schemes can become these stars.
 
We will meet again in Shanghai in April, friends!
 
Liu Bin
DVCon China 2020 General Chair