17 April, 2019

Crowne Plaza Hotel Century Park, Shanghai, China

Using Verification Continuum Platform to Speed PCIe System Verification

Wed, 01/30/2019 - 05:36 -- root

PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels:
- application layer with verification and system performance analysis of applications, drivers and algorithms
- transaction layer
- data link layer for PCIe controller
- full system design, including the PHY layer and PCS and SERDES verification
In this workshop, we will introduce 3 typical solutions: PCIe verification IP (VIP) for System/PCS/SERDES verification, virtual host PCIe solution with ZeBu emulator, and prototyping solution for system validation with HAPS, that enable chip designers to meet the power, performance and area requirements and “shift-left” PCIe verification.

Event ID: 
43e41dcb-5fba-44fa-8d4a-8dac701cc208
Event Type: 
Short Workshop
Location: 
Pudong
Event Time: 
Wednesday, April 17, 2019 -
15:30 to 16:15
Session Number: 
6
Session Number: 
6
Session Number Suffix: 
SW
confID: 
271
Event Sponsor Image URL: 
https://dvcon.org/sites/dvcon.org/files/SynopsysNoTag_WEB.png