Shanghai, China

 

SystemRDL to PSS - Basic to Pro

Wed, 01/22/2020 - 03:58 -- root

Hardware/Software Interface (HSI) plays a key role in the development of SoCs. This interface is best described in a textual format using the SystemRDL – an Accellera Standard. Recently version 2.0 of the SystemRDL has been released. Agnisys will provide detailed hands-on training on SystemRDL and how it impacts the SoC development in many areas – RTL, UVM, Firmware etc.

Attendees will not only learn the details of the language but also have an opportunity to get hands-on with the language compiler to develop some designs. The Workshop will also discuss how to organize a project using SystemRDL, tips and tricks using the language, and best practices in designing the HSI layer. It will also cover writing sequences for the corresponding SystemRDL file and linking to PSS at the end.

The following will be the agenda of the SystemRDL workshop:

  1. Importance of HSI in the SoC development flow
  2. Introduction to SystemRDL 1.0
  3. New constructs in SystemRDL 2.0
  4. Basic properties application (repeat, offset, access, mem, external etc.)
  5. Advanced concepts such as:
    1. Various register buses
    2. Alignment
    3. Addressing (regalign, fullalign, compact)
    4. Interrupt, counter, alias registers
    5. Enum, ispresent
    6. Parameters and Structures
    7. Verification concepts : hdl_path, constraint
  6. Tips and tricks of SystemRDL
  7. Loopholes in the Standard SysmRDL documentation
  8. Corresponding RTL/UVM/CHeader code
  9. UDPs
    1. Multiple bus domain, multiple clock domain, clock domain crossing, etc.
    2. Special registers (lock, shadow, indirect register, trigger buffer, etc.)
    3. Coverage and other UVM properties
  10. Automatic generation from SystemRDL spec
    1. RTL
    2. UVM
    3. C/C++ Header and API
    4. Documentation
  11. Using SystemRDL specification for the creation of sequences
  12. Linking Sequences to PSS (Portable Stimulus Standard)
  13. Best design practices in creating memory map
  14. SystemRDL usage methodology
    1. File organization
    2. Hierarchical specification creation
    3. Use of Git for version control
    4. The Perl Preprocessor
    5. Decoration tags for formatting
    6. Alternative to SystemRDL – pros and cons:
      1. IP-XACT
      2. Word
      3. Excel
      4. CSV
  15. The future of SystemRDL
  16. Hands-On with SystemRDL
    1. Creation of SoC level specification
    2. Best practices for writing the specification
    3. Generation of outputs (RTL/UVM/SV/CHeader/PDF etc.)
    4. Generation of UVM Testbench
    5. Python-Based sequence creation for the specification
    6. Generation of UVM/SV/Firmware outputs
    7. Linking generated sequence file with PSS Summary

The workshop will focus on SystemRDL covering the basics, starting from the keyword to writing a full specification. We will also discuss provide tips, tricks, and a set of guidelines for a good register map. We will see how the specification causes various implications downstream in the various outputs. We will allude to some issues in the current standard and workaround for it. Being a workshop, the audience will be given an opportunity to work on a live example of SystemRDL and compile it to see the different outputs it generates.

Event ID: 
906da36d-3468-4532-b772-f1c8362f048b
Event Type: 
Short Workshop
Location: 
Ballroom A
Event Time: 
Wednesday, April 15, 2020 -
13:15 to 14:00
Session Number: 
1
Session Number: 
1
Session Number Suffix: 
SW
confID: 
299