Smarter Verification – Beyond Brute Force
To optimize development schedules for advanced hardware/software developments, a combination of best in class engines for formal verification, simulation, emulation and FPGA based prototyping is required. Users are carefully optimizing the utilization of verification cycles executed on the various engines. Beyond brute force, beyond simply faster execution, a verification fabric offering verification management, debug, verification IP and portable stimulus for software driven SoC verification is poised to really increase “smartness” of verification and to guide users in their quest to best utilize every verification option they are given, in sequence and in combination. This keynote will introduce the latest trends driving the future of verification and provide a peak into the latest and upcoming improvements in efficient integration of the engines to increase verification productivity.