Leveraging Virtual Prototypes from Concept to Silicon

This tutorial is targeting to describe ARM Models solutions regarding of Virtual Prototype technology. The tutorial will comprise three major parts: ARM Fast model for pre-silicon SW development, ARM Cycle model for System Exploration and Performance analysis, and Hybrid Virtual Prototyping for more use case like SW driven verification. 

ARM Fast Models are accurate, flexible programmer's view models of Arm IP, allowing you to develop software such as drivers, firmware, OS and applications prior to silicon availability. They allow full control over the simulation, including profiling, debug and trace. Fast Models can be exported to SystemC and TLM 2.0, allowing integration into the wider SoC design process. Fast Models are available for all Cortex processors, CCI and CCN interconnect, as well as other system IP. Fast Models are functionally accurate, so banked and co-processor registers, exception levels, translation tables and cache coherency are all available to programmers. 

ARM Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables users to confidently make architectural decisions, optimize performance or develop bare metal software.Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm DS-5. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download.

Fast Model Hybrid simulation connect a CPU subsystem to peripherals on hardware emulators via AMBA transactors for emulation acceleration. Compatible with Cadence, Mentor Graphics and Synopsys emulators for maximum flexibility in your software development and IP validation process. 

The tutorial will benefit not only existing System Level modeling like ESL users, but also show values for end user SW developers, architects, Verification engineers in IC design area.

Event ID: 
Event Type: 
ESL Tutorial
Ballroom B
Event Time: 
Wednesday, April 18, 2018 -
10:45 to 12:15
Session Number: 
Session Number: 
Session Number Suffix: