17 April, 2019

Crowne Plaza Hotel Century Park, Shanghai, China

Enabling Continuously Fast HW/SW co-Design and co-Verification -- Virtual Prototyping & Hybrid Emulation

Wed, 01/30/2019 - 05:36 -- root

Hybrid Emulation: Combining Forces to Accelerate HW/SW Integration and Verification.
The ever growing requirement for computational power is driving increasingly complex SoC hardware design, including the software running on top of the target SoC. The intricacy of the integration and verification of hardware and software represents a big time to market challenge, especially for 5G, AP, AI and ADAS, chips.

Open Virtual/Hybrid System Platform Speed-up the Idea to SW and HW Design

Wed, 01/30/2019 - 05:36 -- root

Virtual System Platform simplifies the creation and support of virtual prototypes with faster debugging. Design teams can begin developing software weeks or months before a hardware prototype is available, and software teams can use it as their application development platform. As part of a connected development flow, the platform can be used to validate the system hardware and software interfaces as the register-transfer level (RTL) becomes available.

Using Verification Continuum Platform to Speed PCIe System Verification

Wed, 01/30/2019 - 05:36 -- root

PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels:
- application layer with verification and system performance analysis of applications, drivers and algorithms
- transaction layer
- data link layer for PCIe controller
- full system design, including the PHY layer and PCS and SERDES verification

Billion-cycle Power Estimation using Fast Emulation

Wed, 01/30/2019 - 05:36 -- root

From high end servers to consumer electronics, SoC development teams are faced with demanding requirements for low power design and the energy efficient operation of devices executing real application workloads. To help avoid problems discovered late in the development cycle, verification engineers are asking important questions:
How can I complete power estimation for real software workloads billions of cycles long?
How can I complete this at the RTL, Gate-level and signoff stages of the design?

Smart FPGA Prototyping for Fast Bring-up on Billion-gate Design

Wed, 01/30/2019 - 05:36 -- root

Protium™ FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.

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