Verification Throughput has become the key challenge of today’s and next generation advanced verification required for Systems on Chips to be successful in a connected world. Users need to run as many cycles as possible in return for their tool and man-power investment. They need to employ smart verification practices to correct as many bugs as early as possible per dollar and day.
5G technologies such as mmWave, MIMO, and beam forming are fundamentally changing the requirements for wireless system design, verification and testing. Traditional divide-and-conquer approaches are no longer enough to achieve verification—full system verification of antenna, RF, and digital is required for design confidence and predictable time-to-market. This keynote will review 5G SoC technologies and related verification challenges that are driving new requirements for verification teams.
We are witnessing a radical change of the way products are created, produced, and utilized. As a consequence of continuing digitalization, leading technology companies are pursuing the idea of a complete, high fidelity “digital twin” that makes the boundaries between the design process of mechanical parts, electronics, embedded software, sensors and specialized IC and sensor technology are disappearing.
Hybrid Emulation: Combining Forces to Accelerate HW/SW Integration and Verification. The ever growing requirement for computational power is driving increasingly complex SoC hardware design, including the software running on top of the target SoC. The intricacy of the integration and verification of hardware and software represents a big time to market challenge, especially for 5G, AP, AI and ADAS, chips. This tutorial will detail Synopsys’ solution to overcome integration and verification challenges with virtual prototyping and hybrid solutions.
Virtual System Platform simplifies the creation and support of virtual prototypes with faster debugging. Design teams can begin developing software weeks or months before a hardware prototype is available, and software teams can use it as their application development platform. As part of a connected development flow, the platform can be used to validate the system hardware and software interfaces as the register-transfer level (RTL) becomes available.
Increased intelligence and autonomy of next-generation transportation products are driving the ICs behind those moving machines to become some of the most advanced semiconductor products in the industry. As a result, this is disrupting how you design, verify and develop these ICs. Starting with design, the entrance of machine learning using neural networks and inference solutions has demonstrated the need to quickly develop these highly algorithmic designs.
PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels:
- application layer with verification and system performance analysis of applications, drivers and algorithms
- transaction layer
- data link layer for PCIe controller
- full system design, including the PHY layer and PCS and SERDES verification
From high end servers to consumer electronics, SoC development teams are faced with demanding requirements for low power design and the energy efficient operation of devices executing real application workloads. To help avoid problems discovered late in the development cycle, verification engineers are asking important questions: How can I complete power estimation for real software workloads billions of cycles long? How can I complete this at the RTL, Gate-level and signoff stages of the design? How can I manage tradeoffs of speed vs. accuracy at each step of my project?
Protium™ FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.
Case Study to understand the bug hunter of Sequential equivalence checking technology