Increased intelligence and autonomy of next-generation transportation products are driving the ICs behind those moving machines to become some of the most advanced semiconductor products in the industry. As a result, this is disrupting how you design, verify and develop these ICs. Starting with design, the entrance of machine learning using neural networks and inference solutions has demonstrated the need to quickly develop these highly algorithmic designs. Validation of those algorithms, performance targets, and power consumption demands new solutions that can simulate the complex, heterogeneous systems with real world interactions. Beyond just ensuring the IC operates correctly, functional safety standards, like ISO 26262 for automotive, are enforcing state-of-the-art practices, strict processes and evidence for compliance to ensure the delivered capabilities are functionally safely. The days of separating functional workflow development from the safety workflow has passed. It is imperative that safety be at the forefront when determining the methodologies and tools to deploy in the creation of your transportation application. The intersection of these challenges is delivering advanced features on-time, within budget all while simultaneously ensuing the IC will not malfunction.
This tutorial we will demonstrate how to use these next-generation IC development practices to build and validate smarter, safer ICs. Specifically, it will look at:
• How to use High-Level Synthesis (HLS) to accelerate the design of smarter IC’s
• How to use emulation to provide a digital twin validation platform beyond just the IC
• How to use develop functionally safe IC’s