17 April, 2019

Crowne Plaza Hotel Century Park, Shanghai, China

Event Details

MP Associates, Inc.
WEDNESDAY April 17, 3:30pm - 4:15pm | Pudong
KEYWORD: APPLICATION BASED DESIGN VERIFICATION CHALLENGES, TECHNIQUES
EVENT TYPE: SHORT WORKSHOP
SESSION 6SW
Using Verification Continuum Platform to Speed PCIe System Verification

Speakers:
Hongzhi Guo - Synopsys, Inc.
Peijun Gong - Synopsys, Inc.
Lin Yang - Synopsys, Inc.
Organizers:
Hongzhi Guo - Synopsys, Inc.
Sward Xie - Synopsys, Inc.
Peijun Gong - Synopsys, Inc.
Lin Yang - Synopsys, Inc.
PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels: - application layer with verification and system performance analysis of applications, drivers and algorithms - transaction layer - data link layer for PCIe controller - full system design, including the PHY layer and PCS and SERDES verification In this workshop, we will introduce 3 typical solutions: PCIe verification IP (VIP) for System/PCS/SERES verification, virtual host PCIe solution with ZeBu emulator, and prototyping solution for system validation with HAPS, that enable chip designers to meet the power, performance and area requirements and “shift-left” PCIe verification.

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