WEDNESDAY April 17, 14:15 - 15:15 | Pudong
EVENT TYPE: REGULAR SESSION
SESSION 6Applications of Sequential Equivalence Checking
Bin "Rocker" Liu - Intel Corp.
Case Study to understand the bug hunter of Sequential equivalence checking technology
|6.1||Observability Analysis of Faults Using Sequential Equivalence Checking|
|Although mutation coverage can point out weakness in the verification environment, the task of analyzing the effect of these non-detected faults and what corrective action to take can be daunting, especially when there are numerous of faults. In this paper, the authors wish to share their experiences in how they applied non-detected faults observability analysis using sequential equivalence checking on 5 real designs and found it useful in saving us time and efforts in the verification signoff process.|
|Speaker:||Penny Yang - Synopsys Taiwan Co., Ltd.
|Authors:||Penny Yang - Synopsys Taiwan Co., Ltd.
Sean Chou - MediaTek, Inc.
Sandeep Jana - Synopsys India Pvt. Ltd.
Yuya Kao - MediaTek, Inc.
Xiaolin Chen - Synopsys, Inc.
|6.2||Applications of Sequential Logic Equivalence Checking|
|Sequential Logic Equivalence Checking verifies functional equivalence between two designs. SLEC is different from traditional Logic Equivalence Checking. The differences between SLEC and LEC are discussed. SLEC has lots of applications and this paper will cover most common usages of SLEC, such as verifying that design behaves the same after optimization, low power clock gating doesn’t break any functions, bug fixes/ECO haven’t injected new bugs, fault tolerance or safety mechanism can detect and fix random faults, backward compatibility, etc. We will provide tricks on how to use SLEC efficiently and improve SLEC convergence rate.|
|Speaker:||Jin Hou - Mentor, A Siemens Business
|Authors:||Jin Hou - Mentor, A Siemens Business
Ping Yeung - Mentor, A Siemens Business