WEDNESDAY April 17, 2:15pm - 3:15pm | Ballroom B
EVENT TYPE: REGULAR SESSION
SESSION 5Verification Strategies 2
Leo Fang - Synopsys, Inc.
More general recommendations for improving your verification process.
|5.1||Modeling Verification Environments using UML diagrams|
|The paper aims into providing overview of UML and showing how it can be utilized to model verification environments developed in an object-oriented programming language, such as SystemVerilog. Usage of UML diagrams improves code understanding and documentation, offering a reusable solution to the problem of representing ever so complex class models found in verification environments. Additional advantage of UML is that it is language agnostic.|
|Speaker:||Darko M. Tomusilovic - VTool Ltd.
|Authors:||Darko M. Tomusilovic - VTool Ltd.
Anja Kokeric - VTool Ltd.
|5.2||A Systematic Approach for Automating the Design and Verification of Power Controllers|
|With increasing complexities in power architecture, design engineers are spending an inordinate amount of time and effort to create designs that support multiple power state combinations. In essence, incorporating power awareness into a design is creating an important bottleneck for achieving timely tape outs. In this paper, we propose a systematic approach to generate power controllers. This systematic approach captures the power and clock intent of the design and enables the design and verification of the power controllers. In summary we believe that our approach would lead to a significant reduction in the design effort for low power designs.|
|Speaker:||Loganath Ramachandran - Accelver Systems Inc.
|Authors:||Shamanth HK - CISMA Consultants Pvt. Ltd.
Loganath Ramachandran - Accelver Systems Inc.