17 April, 2019

Crowne Plaza Hotel Century Park, Shanghai, China

Event Details

MP Associates, Inc.
WEDNESDAY April 17, 2:15pm - 3:15pm | Ballroom B
Verification Strategies 2
Baodong Yu -
Bryan Sniderman -
Stuart Lindsay -
William Chen -
More general recommendations for improving your verification process.

5.1Modeling Verification Environments using UML diagrams
The paper aims into providing overview of UML and showing how it can be utilized to model verification environments developed in an object-oriented programming language, such as SystemVerilog. Usage of UML diagrams improves code understanding and documentation, offering a reusable solution to the problem of representing ever so complex class models found in verification environments. Additional advantage of UML is that it is language agnostic.
 Speaker: Darko M. Tomusilovic - VTool Ltd.
 Authors: Darko M. Tomusilovic - VTool Ltd.
Anja Kokeric - VTool Ltd.
5.2A Systematic Approach for Automating Design and Verification of Power Controllers
With increasing complexities in power architecture, design engineers are spending an inordinate amount of time and effort to develop the design which supports different power state combinations. In essence power aware designing is becoming an important bottleneck for successful and timely tape outs. In this paper we propose a new methodology to automatically generate the power controllers based on the power states and the state transitions required by the designers. This systematic approach captures the power and clock intent of the design, and enables easy design and verification of the power controllers. In summary we believe that our approach would lead to a significant reduction in the design effort focused on power.
 Speaker: Loganath Ramachandran - Accelver Systems Inc.
 Authors: Shamanth HK - CISMA Consultants Pvt. Ltd.
Loganath Ramachandran - Accelver Systems Inc.