WEDNESDAY April 17, 11:15 - 12:15 | Pudong
EVENT TYPE: REGULAR SESSION
SESSION 3Use Cases of Test and Testbench Automation
Bin "Rocker" Liu - Intel Corp.
Solutions to make test and testbench generate automatically.
|3.1||The Power Of Testbench Automation Shortening the Verification Gap For IP Integration|
|UVM based testbench automation, standardization and reusability|
|Speaker:||Yan Wu - Intel Corp.
|Authors:||Yan Wu - Intel Corp.
Yaping Yue - Intel Corp.
Wei Ma - Intel Corp.
|3.2||Application of Nwise Automatic Generation Test Vector Technology in Communication Chip Verification|
|Through the research on the method of reducing the test vector, this paper introduces Nwise method based on mathematical statistical analysis to reduce the test case. At the same time, the method is applied to the communication chip test verification project, which improves the validity and reliability of the construction test vector. After setting the parameters and defining the range by using the Nwise method, run directly in the System Verilog environment. Considering the total number of parameters and the complexity of the constraint relationship between the parameters on the Nwise running time, the parameter ranges can be appropriately split or the number of parameters can be divided into several groups, each parameter groups or ranges use the Nwise package test design separately. According to experimental experience, this method only needs about 20% of the test case equivalent to the complete combination test case.|
|Speaker:||Deyong Yang - Unisoc Communications, Inc.
|Authors:||Shuwei Zhu - Spreadtrum
Deyong Yang - Unisoc Communications, Inc.
Henry Chew - MediaTek, Inc.