Shanghai, China


Event Details

MP Associates, Inc.
WEDNESDAY April 17, 10:15 - 10:45 | Ballroom A & B
Optimizing Verification Throughput for Verification in a Connected World of 5G and AI/ML
Michał Siwiński - Cadence Design Systems, Inc.

Verification Throughput has become the key challenge of today’s and next generation advanced verification required for Systems on Chips to be successful in a connected world. Users need to run as many cycles as possible in return for their tool and man-power investment. They need to employ smart verification practices to correct as many bugs as early as possible per dollar and day. This keynote will outline the key challenges of 5G and AI/ML designs and introduce state of the art verification techniques to increase and scale bare performance of dynamic verification engines, explore how to smartly connect different levels of abstraction and introduce smart bug hunting techniques, allowing users to most efficiently use the verification cycles they spend.

Biography:Michał Siwiński is the Vice President of Product Engineering and Management for the System & Verification Group at Cadence Design Systems. His responsibilities include customer engagement, business development, product portfolio strategy / requirements / priorities, and the ecosystem enablement for the Cadence Verification Suite. The Suite includes JasperGold® formal verification, Xcelium™ parallel simulation, Palladium® emulation, and Protium™ Prototyping core engines. Additionally, it comprehends multi-engines technologies such as Verification IP, Perspec™ tests, Indago™ debug, and vManager™ plan and metrics. Siwiński is also driving verification solutions including Cloud, and flows optimized to address the challenges faced by systems and semi companies across Mobile, Networking, Server, Consumer, Industrial, IoT, Automotive, Aero & Defense, and other verticals, as part of the Cadence System Design Enablement strategy.

Previously at Cadence, Siwiński held various product management, operations, and marketing positions, including responsibilities for functional verification, front-end digital, PCB & IC packaging, and starting Cadence’s IP business.

Siwiński joined Cadence via the acquisition of Verplex Systems, where he was responsible for the formal property checking product line, including product engineering, product validation, technical marketing, and field applications. Prior to Verplex, Siwiński delivered digital design and verification consulting services at Mentor Graphics, Inc.

Siwiński received his Bachelor of Science dual degree in Electrical Engineering and Computer Science from the University of California at Berkeley.