Event Details

MP Associates, Inc.

WEDNESDAY April 18, 5:00pm - 6:00pm | Foyer
EVENT TYPE: POSTER SESSION

SESSION 5
Poster Session
Chairs:
Bin Liu - Intel Corp.
David Zhang - Cadence Design Systems, Inc.
Justin Wang - MediaTek, Inc.
Leo Fang - Synopsys, Inc.
Roman Wang - Advanced Micro Devices, Inc.
Yong Chen - Advanced Micro Devices, Inc.

5.1A Research on the Controllability of Randomization in Verification Environment
 Speaker: Xiaobing Zhang - MediaTek, Inc., hefei, China
 Authors: Guoqing Hu - MediaTek, Inc., hefei, China
Xiaobing Zhang - MediaTek, Inc., hefei, China
Yao Zhan - MediaTek, Inc.
5.2Coverage Driven Clock Domain Crossing Verification
 Speaker: Yuxin You - Mentor, A Siemens Business, Beijing, China
 Authors: Kurt Takara - Mentor, A Siemens Business, Fremont, CA
Chris Kwok - Mentor, A Siemens Business, Fremont, CA
Yuxin You - Mentor, A Siemens Business, Beijing, China
5.3Index based Scoreboard for SATA IP Verification Based on UVM
 Speaker: Linda Cheng - Advanced Micro Devices, Inc., ShangHai, China
 Authors: Linda Cheng - Advanced Micro Devices, Inc., ShangHai, China
Ji Zhibin - Advanced Micro Devices, Inc., Shanghai, China
5.4Development of CAN Bus Protocol Controller Verification IP based on UVM
 Speaker: Zhihua Feng - Institute 706, The Second Academy China Aerospace Science & Industry Corp., China
 Authors: Zhihua Feng - Institute 706, The Second Academy China Aerospace Science & Industry Corp., China
Wei Shen - Northwestern Polytechnical Univ., beijing, China
Dongfang Li - Institute 706, The Second Academy China Aerospace Science & Industry Corp., China
Anping He - Lanzhou University, China
Zhihao Wang - Institute 706, The Second Academy China Aerospace Science & Industry Corp., China
Lirong Chen - Institute 706, The Second Academy China Aerospace Science & Industry Corp.
5.5UVM Registers from the Inside Out
 Speaker: Yuxin You - Mentor, A Siemens Business, Beijing, China
 Authors: Rich Edelman - Mentor, A Siemens Business, Fremont, CA
Yuxin You - Mentor, A Siemens Business, Beijing, China
5.6Advanced UVM Factory Use Cases
 Speaker: Darko M. Tomusilovic - VTool Ltd., Belgrade, Serbia
 Author: Darko M. Tomusilovic - VTool Ltd., Belgrade, Serbia
5.7A Run-time Interactive Scenario Controlling Method
 Speaker: Lingyun Wu - MediaTek, Inc., hefei, China
 Authors: Lingyun Wu - MediaTek, Inc., hefei, China
Mengru Si - MediaTek, Inc., hefei, China
Hongcai Cui - MediaTek, Inc., hefei, China
5.8Create user Adaptive and Reusable UVM Agent by Layered pcie VIP for Non-Standard PCIE Controller Verification
 Speaker: Linda Cheng - Advanced Micro Devices, Inc., ShangHai, China
 Authors: Linda Cheng - Advanced Micro Devices, Inc., ShangHai, China
Ji Zhibin - Advanced Micro Devices, Inc., Shanghai, China
5.9A Practical XOR Self-Gating Method for Dynamic Power Saving
 Speaker: Chai Yihua - Intel Corp., xi'an, China
 Authors: Chai Yihua - Intel Corp., xi'an, China
Yang Wang - Intel Corp., xi'an, China
5.10MCERTL: Mutation-based Correction Engine For RTL Designs
 Speaker: Khaled . Mohamed - Mentor, A Siemens Business, cairo, Egypt
 Author: Khaled . Mohamed - Mentor, A Siemens Business, cairo, Egypt
5.11Designing a hybrid functional coverage to enhance SoC verification
 Speaker: Peng Zhang - Advanced Micro Devices, Inc., shanghai, China
 Authors: Peng Zhang - Advanced Micro Devices, Inc., shanghai, China
Zhiwen Zhang - Advanced Micro Devices, Inc., Shanghai, China
5.12Built a Novel Marvell Ethernet PHY Chip Verification Platform Basing on the Marvell Unique Centralized-Management Methodology/block Architecture and the Random Stimulus Input Variable Table Idea
 Speaker: Peter Wang - Marvell Semiconductor, Inc., Santa Clara, CA
 Author: Peter Wang - Marvell Semiconductor, Inc., Santa Clara, CA
5.13Automated Formal Verification of SystemC/C++ High-Level Synthesis Models
 Speaker: Vladislav Palfy - OneSpin Solutions GmbH, Munich, Germany
 Authors: Sergio Marchese - OneSpin Solutions GmbH, Bristol, United Kingdom
Sven Beyer - OneSpin Solutions GmbH, Munich, Germany
Vladislav Palfy - OneSpin Solutions GmbH, Munich, Germany
5.14Hierarchical Clock Domain Crossing Methodology for Reconvergence Closure on Complex SoCs
 Speaker: Aditya Vij - Mentor, A Siemens Business, Noida, India
 Authors: Aditya Vij - Mentor, A Siemens Business, Noida, India
Apoorv Aggarwal - Advanced Micro Devices, Inc., Hyderabad, India