Event Details

MP Associates, Inc.
WEDNESDAY April 18, 4:00pm - 5:00pm | Ballroom A
EVENT TYPE: REGULAR SESSION
SESSION 3
Memory Design and Verification
Chair:
Jun Tao - Fudan Univ.
DRAM memory controllers have gained a lot of popularity in recent years. They are widely used in applications ranging from smart phones to high performance computers. These applications requires large amount of memory accessing. However, memorywall is still a bottleneck. In this session part1, we introduce the most recent techniques used to enhance DRAM Memory controllers in terms of power, capacity, latency and bandwidth. In this session part2 we cover register && memory sequence seamless reuse in IP and SoC verification.

3.1Techniques to Enhance DRAM Memory Controllers: Industrial Experiences
 Speaker: Khaled . Mohamed - Mentor, A Siemens Business, cairo, Egypt
 Author: Khaled . Mohamed - Mentor, A Siemens Business, cairo, Egypt
3.2Making Register and Memory Sequence Seamless Reuse in IP and SoC UVM Verification
 Speaker: Roman Wang - Advanced Micro Devices, Inc., shanghai, China
 Author: Roman Wang - Advanced Micro Devices, Inc., shanghai, China