Event Details

MP Associates, Inc.

WEDNESDAY April 18, 2:45pm - 3:45pm | Ballroom A
EVENT TYPE: REGULAR SESSION

SESSION 1
Verification Methodology: Formal & Emulator
Chairs:
Ajeetha Kumari - CVC Pvt., Ltd.
Roman Wang - Advanced Micro Devices, Inc.
Verification methodology is getting more and more important when it comes to IP&& SoC verification. In this session we will discuss Formal verification && Emulator methodology. the one big challenge for Formal verification is how to handle inconclusive assertion. In this session part1, we cover the methodology and experience how to close inconclusive assertion proven. Hardware accelerator is commonly used more and more in a lot of company. In this session part2, we cover how to conquer complex SOC test sequences with Emulator.

1.1Handling Inconclusive Assertions in Formal Verification
 Speaker: Yuxin You - Mentor, A Siemens Business, Beijing, China
 Authors: Jin Hou - Mentor, A Siemens Business, Fremont, CA
Mark Eslinger - Mentor, A Siemens Business, Fremont, CA
Ping Yeung - Mentor, A Siemens Business, Fremont, CA
Yuxin You - Mentor, A Siemens Business, Beijing, China
1.2Improving Verification of High-Level Synthesis IP with Sequential Equivalence Checking
The productivity advantages of high-level synthesis (HLS) makes design becomes more broadly reusable, because the designer can direct the HLS tool to use the same SystemC source code to target different power, performance, and area (PPA) targets, different technology libraries, or devices (ASIC vs FPGA). However, design productivity is only one part of the equation. The verification effort often far exceeds the design effort. That is especially true when retargeting intellectual property generated with HLS (HLS IP). Although the original source code is the same, the RTL is completely different. So while the design time is nearly zero, the verification time is nearly the same as before. This paper introduces the idea of using sequential equivalence checking (SEC) with HLS to formally prove that the original verified RTL is functionally equivalent to a new RTL implementation targeted towards different PPA targets, technology libraries, or devices.
 Speaker: Xingri Li - Cadence Design Systems, Inc., Yokohama, Japan
 Authors: Xingri Li - Cadence Design Systems, Inc., Yokohama, Japan
Dave Pursley - Cadence Design Systems, Inc., Pittsburgh, PA