Shanghai, China


2019 Call for Tutorials

2019 Call for Tutorials

ESL Track Submissions

DVCon China solicits detailed proposals for tutorials that are highly technical and reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools.

The ESL track aims to accelerate the adoption of SystemC in the Semiconductor Industry. It provides a platform for the SystemC beginners, SystemC/TLM experts, ESL managers and ESL vendors to share their knowledge, experiences & best practices about SystemC usage. Submissions are encouraged in (but not restricted to) the following topics:

  • Virtual-Platforms and System-Level Design
    • Transaction-level modeling for system-level design
    • Hardware/software/embedded co-design
    • System-level design techniques, flows and methodologies
    • High-level synthesis from ESL languages
  • Power
    • Low Power Design
    • Power estimation techniques
    • Power modeling
  • Mixed-Signal (AMS)
    • SystemC AMS usage for mixed-signal simulation
    • AMS system-level and concept design


DV Track Submissions

In the DV Track we are soliciting detailed proposals for tutorials from industry leaders in the field of Design & Verification. The DV Track provides a platform for the wide Design-Verification community including beginners, intermediate and seniors to learn the latest concepts, techniques, etc. in their respective domains of interest. Submissions are encouraged in (but not restricted to) the following topics:

  • UVM – Universal Verification Methodology
  • Latest language developments in SystemVerilog including:
    • New and enhanced constructs
    • Assertion enhancements
  • Advanced stimulus generation methods, reuse of stimulus across levels of verification (Portable Stimulus)
  • Software-driven and reusable verification
  • Formal Verification
    • Coding styles, techniques for assertions for formal
    • Model Checking techniques, target designs/blocks
  • Debug automation through transaction-level debug, smart tricks to handle performance issues, faster time to debug techniques
  • Low Power intent verification through standards such as UPF and related technologies
  • Use of IPXACT, SystemRDL in design flow
  • Digital and Analog Mixed Signal (AMS) techniques
  • Emulation, Acceleration, Prototyping



Submission Guidelines

The following will be required in order to submit a proposal:

  • A title.
  • Name, affiliation, phone number and email addresses for all speakers.
  • An introduction that specifies the context and motivation of the tutorial submission.
  • A summary of the specific content of your tutorial and your intended audience. For each presentation, mention the title and a short paragraph description.
  • Must be descriptive enough to see what this tutorial will address and what the attendees would learn from it
  • Proposal should be approximately 500-1000 words (English or Chinese).

There is no template for the proposal



  • December 10 - EXTENDED: Tutorial submission deadline
  • December 11: Tutorial accept/reject notification
  • January 10: Deadline to submit final tutorial description, title, and presenter information for DVCon China website and publications
  • March 19: Draft Presentation Slides Due to Tutorial Chair for Review
  • April 3: Final Presentations Slides Due for Proceedings
  • April 17: DVCon China 2019 conference