From high end servers to consumer electronics, SoC development teams are faced with demanding requirements for low power design and the energy efficient operation of devices executing real application workloads. To help avoid problems discovered late in the development cycle, verification engineers are asking important questions: How can I complete power estimation for real software workloads billions of cycles long? How can I complete this at the RTL, Gate-level and signoff stages of the design? How can I manage tradeoffs of speed vs. accuracy at each step of my project? How can I manage huge data-sets and perform all the calculation that I need? How can I find the peak power from a billion-cycle test, and know I have the peak? What is this SAIF thing that the power team keeps asking me for and why do I care? Want to learn more? In this workshop we provide an introduction to billion-cycle power estimation and how fast emulation with Synopsys ZeBu Server can solve tough problems on today’s large designs. We will review the methods of power estimation at various phases of the project, from concept to RTL to Gate-level signoff, and the tradeoffs needed at each step of the flow to meet your power budget. We will examine new technology available to estimate power using Synopsys ZeBu Server including peak power over millions of cycles, average power for very long tests, and signoff power with close silicon accuracy.
Billion-cycle Power Estimation using Fast Emulation
Wednesday, April 17, 2019 -
15:30 to 16:15
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